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| author | sdlyyxy <sdlyyxy@icloud.com> | 2023-07-14 11:10:43 +0200 |
|---|---|---|
| committer | Pauli <pauli@openssl.org> | 2023-07-21 02:19:19 +0200 |
| commit | 08e6eb216c9d65d502dc136a40e1c0adaefab759 (patch) | |
| tree | 420395c61f041bcde8a3a3f4d9dfa2948cf0acb5 /crypto/armcap.c | |
| parent | Enable ARMv8.2 accelerated SHA3 on compatible Apple CPUs (diff) | |
| download | openssl-08e6eb216c9d65d502dc136a40e1c0adaefab759.tar.xz openssl-08e6eb216c9d65d502dc136a40e1c0adaefab759.zip | |
Move CPU detection to armcap.c
Reviewed-by: Tom Cosgrove <tom.cosgrove@arm.com>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/21398)
Diffstat (limited to 'crypto/armcap.c')
| -rw-r--r-- | crypto/armcap.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/crypto/armcap.c b/crypto/armcap.c index 03bc659bdb..8443f8fcbd 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -300,6 +300,7 @@ void OPENSSL_cpuid_setup(void) ((strncmp(uarch, "Apple M1", 8) == 0) || (strncmp(uarch, "Apple M2", 8) == 0))) { OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; + OPENSSL_armcap_P |= ARMV8_WORTH_USING_SHA3; } } } @@ -419,6 +420,20 @@ void OPENSSL_cpuid_setup(void) MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; + if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)) && + (OPENSSL_armcap_P & ARMV8_SHA3)) + OPENSSL_armcap_P |= ARMV8_WORTH_USING_SHA3; # endif } #endif /* _WIN32, __ARM_MAX_ARCH__ >= 7 */ |