diff options
| author | Andy Polyakov <appro@openssl.org> | 2017-12-04 14:03:05 +0100 |
|---|---|---|
| committer | Andy Polyakov <appro@openssl.org> | 2017-12-08 12:57:09 +0100 |
| commit | 79337628702dc5ff5570f02d6b92eeb02a310e18 (patch) | |
| tree | 6d8c70ad956ebf9ce58b612231eb04f0e485121f /crypto/x86_64cpuid.pl | |
| parent | Leave a message in doc to indicate 0 is not acceptable (diff) | |
| download | openssl-79337628702dc5ff5570f02d6b92eeb02a310e18.tar.xz openssl-79337628702dc5ff5570f02d6b92eeb02a310e18.zip | |
crypto/x86_64cpuid.pl: suppress AVX512F flag on Skylake-X.
It was observed that AVX512 code paths can negatively affect overall
Skylake-X system performance. But we are talking specifically about
512-bit code, while AVX512VL, 256-bit variant of AVX512F instructions,
is supposed to fly as smooth as AVX2. Which is why it remains unmasked.
Reviewed-by: Rich Salz <rsalz@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/4838)
Diffstat (limited to 'crypto/x86_64cpuid.pl')
| -rw-r--r-- | crypto/x86_64cpuid.pl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/crypto/x86_64cpuid.pl b/crypto/x86_64cpuid.pl index d30928efbd..0a88c7a4ed 100644 --- a/crypto/x86_64cpuid.pl +++ b/crypto/x86_64cpuid.pl @@ -139,6 +139,7 @@ OPENSSL_ia32_cpuid: .Lnocacheinfo: mov \$1,%eax cpuid + movd %eax,%xmm0 # put aside processor id and \$0xbfefffff,%edx # force reserved bits to 0 cmp \$0,%r9d jne .Lnotintel @@ -186,6 +187,13 @@ OPENSSL_ia32_cpuid: jc .Lnotknights and \$0xfff7ffff,%ebx # clear ADCX/ADOX flag .Lnotknights: + movd %xmm0,%eax # restore processor id + and \$0x0fff0ff0,%eax + cmp \$0x00050650,%eax # Skylake-X + jne .Lnotskylakex + and \$0xfffeffff,%ebx # ~(1<<16) + # suppress AVX512F flag on Skylake-X +.Lnotskylakex: mov %ebx,8(%rdi) # save extended feature flags mov %ecx,12(%rdi) .Lno_extended_info: |