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| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-05-08 10:42:20 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 10:55:46 +0200 |
| commit | b7f720d68c0042cc8ce496e31a61df79a77f1b48 (patch) | |
| tree | f53474f89918485af4bb81cc1c188d5eff41e377 /arch/mips/alchemy/mtx-1/board_setup.c | |
| parent | MIPS: Alchemy: Cleanup DMA addresses (diff) | |
| download | linux-b7f720d68c0042cc8ce496e31a61df79a77f1b48.tar.xz linux-b7f720d68c0042cc8ce496e31a61df79a77f1b48.zip | |
MIPS: Alchemy: Clean up GPIO registers and accessors
remove au_readl/au_writel, remove the predefined GPIO1/2 KSEG1 register
addresses and fix the fallout in all boards and drivers.
This also fixes a bug in the mtx-1_wdt driver which was introduced by
commit 6ea8115bb6f359df4f45152f2b40e1d4d1891392
("Convert mtx1 wdt to be a platform device and use generic GPIO API")
before this patch mtx-1_wdt only modified GPIO215, the patch then
used the gpio resource information as bit index into the GPIO2 register
but the conversion to the GPIO API didn't realize that.
With this patch the drivers original behaviour is restored and GPIO15
is left alone.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
Cc: Florian Fainelli <florian@openwrt.org>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: linux-watchdog@vger.kernel.org
Cc: Wim Van Sebroeck <wim@iguana.be>
Patchwork: https://patchwork.linux-mips.org/patch/2381/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org
Diffstat (limited to 'arch/mips/alchemy/mtx-1/board_setup.c')
| -rw-r--r-- | arch/mips/alchemy/mtx-1/board_setup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cf436ab679ae..3ae984cf98cf 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -87,7 +87,7 @@ void __init board_setup(void) au_writel(SYS_PF_NI2, SYS_PINFUNC); /* Initialize GPIO */ - au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); + au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ |