diff options
| author | Vincent Chen <vincent.chen@sifive.com> | 2021-03-22 15:26:05 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-04-26 17:24:57 +0200 |
| commit | 800149a77c2cb8746a94457939b1ba1e37d2c14e (patch) | |
| tree | a31cd1e131fc9259b2d7a12b62fe5958587b420b /arch/riscv/include/asm/errata_list.h | |
| parent | riscv: sifive: Add SiFive alternative ports (diff) | |
| download | linux-800149a77c2cb8746a94457939b1ba1e37d2c14e.tar.xz linux-800149a77c2cb8746a94457939b1ba1e37d2c14e.zip | |
riscv: sifive: Apply errata "cip-453" patch
Add sign extension to the $badaddr before addressing the instruction page
fault and instruction access fault to workaround the issue "cip-453".
To avoid affecting the existing code sequence, this patch will creates two
trampolines to add sign extension to the $badaddr. By the "alternative"
mechanism, these two trampolines will replace the original exception
handler of instruction page fault and instruction access fault in the
excp_vect_table. In this case, only the specific SiFive CPU core jumps to
the do_page_fault and do_trap_insn_fault through these two trampolines.
Other CPUs are not affected.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/include/asm/errata_list.h')
| -rw-r--r-- | arch/riscv/include/asm/errata_list.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 1b56131431c9..6148d34d4245 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -5,8 +5,27 @@ #ifndef ASM_ERRATA_LIST_H #define ASM_ERRATA_LIST_H +#include <asm/alternative.h> +#include <asm/vendorid_list.h> + #ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_NUMBER 0 +#define ERRATA_SIFIVE_CIP_453 0 +#define ERRATA_SIFIVE_NUMBER 1 #endif +#ifdef __ASSEMBLY__ + +#define ALT_INSN_FAULT(x) \ +ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \ + __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \ + SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ + CONFIG_ERRATA_SIFIVE_CIP_453) + +#define ALT_PAGE_FAULT(x) \ +ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \ + __stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \ + SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \ + CONFIG_ERRATA_SIFIVE_CIP_453) +#endif /* __ASSEMBLY__ */ + #endif |