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| author | Atish Patra <atishp@rivosinc.com> | 2024-04-20 17:17:18 +0200 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-04-22 07:43:44 +0200 |
| commit | 5d4acb7f2e1af1a5160870dbd11d2bd3a86007ed (patch) | |
| tree | 46f81525558551582ccfc7696eaf3e8ff7931939 /arch/riscv/include/asm/sbi.h | |
| parent | RISC-V: Fix the typo in Scountovf CSR name (diff) | |
| download | linux-5d4acb7f2e1af1a5160870dbd11d2bd3a86007ed.tar.xz linux-5d4acb7f2e1af1a5160870dbd11d2bd3a86007ed.zip | |
RISC-V: Add FIRMWARE_READ_HI definition
SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.
Add the definition for that function.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-3-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm/sbi.h')
| -rw-r--r-- | arch/riscv/include/asm/sbi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..ef8311dafb91 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; union sbi_pmu_ctr_info { |