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| author | Dan Williams <dan.j.williams@intel.com> | 2021-05-14 07:22:00 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-05-15 01:13:19 +0200 |
| commit | 5f653f7590ab7db7379f668b2975744585206b0d (patch) | |
| tree | 94a35fdd5f2d6c58594d24933b5cfa66523243d4 /drivers/cxl/Makefile | |
| parent | cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices (diff) | |
| download | linux-5f653f7590ab7db7379f668b2975744585206b0d.tar.xz linux-5f653f7590ab7db7379f668b2975744585206b0d.zip | |
cxl/core: Rename bus.c to core.c
In preparation for more generic shared functionality across endpoint
consumers of core cxl resources, and platform-firmware producers of
those resources, rename bus.c to core.c. In addition to the central
rendezvous for interleave coordination, the core will also define common
routines like CXL register block mapping.
Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162096972018.1865304.11079951161445408423.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/Makefile')
| -rw-r--r-- | drivers/cxl/Makefile | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index a314a1891f4d..3808e39dd31f 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_CXL_BUS) += cxl_bus.o +obj-$(CONFIG_CXL_BUS) += cxl_core.o obj-$(CONFIG_CXL_MEM) += cxl_mem.o ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL -cxl_bus-y := bus.o +cxl_core-y := core.o cxl_mem-y := mem.o |