summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/Makefile (follow)
Commit message (Expand)AuthorAgeFilesLines
* cxl/port: Fix CXL port initialization order when the subsystem is built-inDan Williams2024-10-251-6/+14
* cxl/pmem: Introduce nvdimm_security_ops with ->get_flags() operationDave Jiang2022-12-011-1/+1
* PM: CXL: Disable suspendDan Williams2022-04-231-1/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-091-0/+2
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-091-0/+2
* cxl: Rename CXL_MEM to CXL_PCIBen Widawsky2022-02-091-1/+1
* cxl: Move cxl_core to new directoryBen Widawsky2021-08-061-3/+1
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-161-0/+2
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-101-0/+2
* cxl: Rename mem to pciBen Widawsky2021-05-261-2/+2
* cxl/core: Rename bus.c to core.cDan Williams2021-05-151-2/+2
* cxl/mem: Register CXL memX devicesDan Williams2021-02-171-0/+3
* cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpointsDan Williams2021-02-171-0/+4