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| author | Imre Deak <imre.deak@intel.com> | 2022-04-14 23:06:53 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-04-20 19:42:12 +0200 |
| commit | 979e1b32e0e202197f182ec0abfadecbdd53b1ec (patch) | |
| tree | 6e1619c960caef1e2f23adb717b7a850ecc41726 /drivers/gpu/drm/i915/display/intel_display_power.h | |
| parent | drm/i915: Sanitize the ADL-S power well definition (diff) | |
| download | linux-979e1b32e0e202197f182ec0abfadecbdd53b1ec.tar.xz linux-979e1b32e0e202197f182ec0abfadecbdd53b1ec.zip | |
drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.
This also allows for removing the aliasing in enum values in a follow-up
patch.
v2: Add the functions to intel_display_power.c, use
intel_display_power_ prefix.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414210657.1785773-14-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 66fef12ef3db..2ea30a4cfaa8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -8,8 +8,10 @@ #include "intel_runtime_pm.h" +enum aux_ch; enum dpio_channel; enum dpio_phy; +enum port; struct drm_i915_private; struct i915_power_well; struct intel_encoder; @@ -130,6 +132,7 @@ enum intel_display_power_domain { POWER_DOMAIN_INIT, POWER_DOMAIN_NUM, + POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, }; #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) @@ -266,6 +269,15 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915, void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); +enum intel_display_power_domain +intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port); +enum intel_display_power_domain +intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port); +enum intel_display_power_domain +intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); +enum intel_display_power_domain +intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); + /* * FIXME: We should probably switch this to a 0-based scheme to be consistent * with how we now name/number DBUF_CTL instances. |