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path: root/arch/riscv/include/asm/cpufeature.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* riscv: cpufeature: Extract common elements from extension checkingCharlie Jenkins2024-07-231-34/+44
* riscv: Extend cpufeature.c to detect vendor extensionsCharlie Jenkins2024-07-231-0/+25
* riscv: add ISA extensions validation callbackClément Léger2024-06-261-0/+1
* Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2024-03-221-12/+19
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| * riscv: Set unaligned access speed at compile timeCharlie Jenkins2024-03-131-11/+13
| * riscv: Decouple emulated unaligned accesses from access speedCharlie Jenkins2024-03-131-1/+1
| * riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins2024-03-131-3/+8
* | work around gcc bugs with 'asm goto' with outputsLinus Torvalds2024-02-101-2/+2
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* Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt2024-01-181-0/+2
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| * riscv: Add static key for misaligned accessesCharlie Jenkins2024-01-181-0/+2
* | riscv: add ISA extension parsing for scalar cryptoEvan Green2023-12-131-1/+3
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* riscv: Rearrange hwcap.h and cpufeature.hXiao Wang2023-11-091-0/+83
* RISC-V: Probe misaligned access speed in parallelEvan Green2023-11-081-1/+0
* Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-051-0/+18
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| * riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-011-0/+18
* | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-211-0/+1
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* RISC-V: Probe for unaligned access speedEvan Green2023-09-011-0/+2
* RISC-V: Track ISA extensions per hartEvan Green2023-06-191-0/+10
* RISC-V: hwprobe: Support probing of misaligned access performanceEvan Green2023-04-191-0/+2
* RISC-V: Move struct riscv_cpuinfo to new headerEvan Green2023-04-191-0/+21