summaryrefslogtreecommitdiffstats
path: root/drivers/clk/at91 (follow)
Commit message (Expand)AuthorAgeFilesLines
*-. Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-nextStephen Boyd2024-09-216-35/+1026
|\ \
| | * clk: at91: sama7g5: Allocate only the needed amount of memory for PLLsClaudiu Beznea2024-08-241-2/+3
| | * clk: at91: sam9x7: add sam9x7 pmc driverVarshini Rajendran2024-08-072-0/+947
| | * clk: at91: sama7g5: move mux table macros to header fileVarshini Rajendran2024-08-072-25/+26
| | * clk: at91: sam9x7: add support for HW PLL freq dividersVarshini Rajendran2024-08-072-2/+29
| | * clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputsVarshini Rajendran2024-08-074-6/+21
| |/
* / clk: at91: Use of_property_count_u32_elems() to get property lengthRob Herring (Arm)2024-08-031-2/+3
|/
* clk: at91: remove unnecessary conditionsDan Carpenter2023-10-191-7/+5
*-. Merge branches 'clk-qcom' and 'clk-microchip' into clk-nextStephen Boyd2023-06-2722-523/+730
|\ \
| | * clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_idClaudiu Beznea2023-06-211-1/+1
| | * clk: at91: sama7g5: switch to parent_hw and parent_dataClaudiu Beznea2023-06-211-342/+454
| | * clk: at91: sckc: switch to parent_data/parent_hwClaudiu Beznea2023-06-211-27/+48
| | * clk: at91: clk-sam9x60-pll: add support for parent_hwClaudiu Beznea2023-06-214-9/+17
| | * clk: at91: clk-utmi: add support for parent_hwClaudiu Beznea2023-06-2110-17/+28
| | * clk: at91: clk-system: add support for parent_hwClaudiu Beznea2023-06-2114-19/+24
| | * clk: at91: clk-programmable: add support for parent_hwClaudiu Beznea2023-06-2114-17/+21
| | * clk: at91: clk-peripheral: add support for parent_hwClaudiu Beznea2023-06-2114-23/+34
| | * clk: at91: clk-master: add support for parent_hwClaudiu Beznea2023-06-2114-35/+47
| | * clk: at91: clk-generated: add support for parent_hwClaudiu Beznea2023-06-216-7/+15
| | * clk: at91: clk-main: add support for parent_data/parent_hwClaudiu Beznea2023-06-2114-37/+52
| |/
* | clk: at91: smd: Switch to determine_rateMaxime Ripard2023-06-091-12/+17
* | clk: at91: sckc: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
* | clk: at91: main: Add a determine_rate hookMaxime Ripard2023-06-091-0/+1
|/
* clk: at91: clk-sam9x60-pll: fix return value checkClaudiu Beznea2023-03-061-1/+1
* clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60Claudiu Beznea2023-01-091-8/+8
* clk: at91: mark ddr clocks as criticalClaudiu Beznea2023-01-0915-43/+131
* ARM: at91: rm9200: fix usb device clock idMichael Grzeschik2022-11-171-1/+1
* Merge branch 'clk-rate-range' into clk-nextStephen Boyd2022-10-143-7/+11
|\
| * clk: Stop forwarding clk_rate_requests to the parentMaxime Ripard2022-09-153-7/+11
| |
| \
*-. \ Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner...Stephen Boyd2022-10-041-0/+10
|\ \ \ | | |/ | |/|
| | * clk: at91: sama5d2: Add Generic Clocks for UART/USARTSergiu Moga2022-09-151-0/+10
| |/
* / clk: at91: dt-compat: Hold reference returned by of_get_parent()Liang He2022-08-191-24/+84
|/
* clk: at91: generated: consider range when calculating best rateCodrin Ciubotariu2022-05-171-0/+4
*-. Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' in...Stephen Boyd2022-03-291-1/+1
|\ \
| | * clk: cleanup commentsTom Rix2022-03-121-1/+1
| |/
* | clk: at91: clk-master: remove dead codeClaudiu Beznea2022-03-0813-134/+18
* | clk: at91: sama7g5: fix parents of PDMCs' GCLKCodrin Ciubotariu2022-03-081-4/+4
* | clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus2022-01-251-1/+7
* | clk: at91: allow setting PMC_AUDIOPINCK clock parents via DTZixun LI2022-01-251-1/+3
|/
* clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea2021-10-271-1/+1
* clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea2021-10-271-10/+1
* clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-2713-82/+186
* clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea2021-10-274-29/+95
* clk: at91: clk-master: fix prescaler logicClaudiu Beznea2021-10-271-1/+1
* clk: at91: clk-master: mask mckr against layout->maskClaudiu Beznea2021-10-271-2/+5
* clk: at91: clk-master: check if div or pres is zeroClaudiu Beznea2021-10-271-2/+2
* clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULLClaudiu Beznea2021-10-271-2/+2
* clk: at91: pmc: add sama7g5 to the list of available pmcsClaudiu Beznea2021-10-271-2/+3
* clk: at91: clk-master: improve readability by using local variablesClaudiu Beznea2021-10-271-3/+3
* clk: at91: clk-master: add register definition for sama7g5's master clockClaudiu Beznea2021-10-271-27/+23
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 08:33:11 +0100