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path: root/drivers/clk/imx (follow)
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* clk: imx: Align imx sc clock parent msg structs to 4Leonard Crestez2020-03-261-1/+1
* clk: imx: Align imx sc clock msg structs to 4Leonard Crestez2020-03-261-3/+3
* clk: imx8mp: Correct the enet_qos parent clockFugang Duan2020-03-161-1/+1
* clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parentAnson Huang2020-03-161-1/+1
*-. Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '...Stephen Boyd2020-01-3121-1052/+1978
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| * | clk: imx: Add support for i.MX8MP clock driverAnson Huang2020-01-123-0/+771
| * | clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based APIAnson Huang2020-01-121-2/+5
| * | clk: imx: imx8mq: Switch to clk_hw based APIPeng Fan2019-12-231-281/+292
| * | clk: imx: imx8mm: Switch to clk_hw based APIPeng Fan2019-12-231-271/+284
| * | clk: imx: imx8mn: Switch to clk_hw based APIPeng Fan2019-12-231-238/+251
| * | clk: imx: Remove __init for imx_obtain_fixed_clk_hw() APIPeng Fan2019-12-231-2/+2
| * | clk: imx: gate3: Switch to clk_hw based APIPeng Fan2019-12-231-2/+5
| * | clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan2019-12-231-0/+10
| * | clk: imx: add imx_unregister_hw_clocksPeng Fan2019-12-232-0/+9
| * | clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan2019-12-232-9/+24
| * | clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan2019-12-232-9/+20
| * | clk: imx7up: Rename the clks to hwsAbel Vesa2019-12-111-91/+91
| * | clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa2019-12-113-6/+6
| * | clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw basedAbel Vesa2019-12-113-10/+10
| * | clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw basedAbel Vesa2019-12-113-4/+4
| * | clk: imx: Rename sccg and frac pll register to suggest clk_hwAbel Vesa2019-12-113-7/+16
| * | clk: imx: imx7ulp composite: Rename to show is clk_hw basedAbel Vesa2019-12-113-28/+28
| * | clk: imx: pllv2: Switch to clk_hw based APIAbel Vesa2019-12-112-6/+13
| * | clk: imx: pllv1: Switch to clk_hw based APIAbel Vesa2019-12-112-6/+13
| * | clk: imx: Replace all the clk based helpers with macrosAbel Vesa2019-12-111-27/+12
| * | clk: imx: Rename the SCCG to SSCGAbel Vesa2019-12-114-81/+81
| * | clk: imx: Add correct failure handling for clk based helpersAbel Vesa2019-12-111-15/+22
| * | clk: imx8qxp-lpcg: Warn against devm_platform_ioremap_resourceLeonard Crestez2019-12-111-0/+11
| * | clk: imx8mn: correct the usb1_ctrl parent to be usb_busLi Jun2019-12-111-1/+1
| * | clk: imx8m: Suppress bind attrsLeonard Crestez2019-12-093-0/+15
| * | clk: imx7ulp: Fix watchdog2 clock name typoFabio Estevam2019-12-091-1/+1
| * | clk: imx6q: disable non functional dividerJan Remmet2019-12-091-1/+4
| * | clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez2019-12-094-2/+10
| * | clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocksLeonard Crestez2019-12-093-8/+23
| * | clk: imx: clk-divider-gate: drop redundant initializationPeng Fan2019-12-091-4/+4
| * | clk: imx: clk-divider-gate: fix a typo in commentPeng Fan2019-12-091-1/+1
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* | clk: imx: pll14xx: fix clk_pll14xx_wait_lockPeng Fan2019-12-111-1/+1
* | clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_tablePeng Fan2019-12-091-0/+1
* | clk: imx: clk-composite-8m: add lock to gate/muxPeng Fan2019-12-091-0/+2
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-12-0210-301/+208
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| *-. Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'c...Stephen Boyd2019-11-2710-287/+208
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| | | * clk: imx: imx8mq: fix sys3_pll_out_selsPeng Fan2019-11-041-2/+2
| | | * clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clockFancy Fang2019-10-281-2/+1
| | | * clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-4/+4
| | | * clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-6/+6
| | | * clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-4/+4
| | | * clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify codePeng Fan2019-10-281-2/+2
| | | * clk: imx7ulp: Correct DDR clock mux optionsAnson Huang2019-10-261-2/+2
| | | * clk: imx7ulp: Correct system clock source option #7Anson Huang2019-10-261-1/+1
| | | * clk: imx: imx8mq: mark sys1/2_pll as fixed clockPeng Fan2019-10-251-6/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 06:49:33 +0100